FIG. 15 is a plan view illustrating a conventional active matrix substrate. As illustrated in FIG. 15, in each pixel area 50, its pixel electrode 51 is surrounded by a scanning signal line 52 for supplying a scanning signal, and a data signal line 53 for supplying a data signal. The scanning signal line 52 and the data signal line 53 intersect each other. Further, a TFT (Thin Film Transistor) 54 is provided at an intersection of the scanning signal line 52 and the data signal line 53. The scanning signal line 52 is connected to a gate electrode 55 of the TFT 54, and driving of the TFT 54 is controlled by the scanning signal inputted into the gate electrode 55. The data signal line 53 is connected to a source electrode 66a of the TFT 54, and the data signal is inputted into the source electrode 66a. Further, a drain lead-out wire 56 is connected to a drain electrode 66b of the TFT 54. Furthermore, a storage capacitor wire 59 is provided in the pixel area 50 so as to (i) prevent a liquid crystal layer from self-discharging while the TFT is off, (ii) prevent picture signal deterioration caused by off-current of the TFT, and (iii) be used, for example, as a pathway of various modulation signals for driving liquid crystal.
The drain electrode 66b of the TFT 54 is connected to a storage capacitor electrode 57 (a drain lead-out electrode) via the drain lead-out wire 56, which storage capacitor electrode 57 overlaps with the storage capacitor wire 59. The storage capacitor electrode 57 is connected to the pixel electrode 51 via a contact hole 58. The storage capacitor electrode 57 (the drain lead-out electrode) and the storage capacitor wire 59 form a storage capacitor in cooperation.
FIG. 16(a) is a cross-sectional view illustrating the conventional active matrix substrate with the contact hole. FIG. 16(b) is a cross-sectional view illustrating the conventional active matrix substrate including a driver connecting terminal.
As illustrated in FIG. 16(a), in the vicinity of the contact hole in the pixel area, the storage capacitor wire 59, a gate insulating film 81, the drain lead-out electrode 57, an interlayer insulating film 87, and the pixel electrode 51 are formed on a substrate 80 in this order. An area of the interlayer insulating film 87 is removed (etched away), to which area the contact hole is to be formed, so as to form the contact hole 58. This connects the pixel electrode 51 with the drain electrode 57.
Meanwhile, in the vicinity of the driver connecting terminal located at an edge of the active matrix substrate, as illustrated in FIG. 16(b), a driver connecting terminal 90, a gate insulating film 81, and the interlayer insulating film 87 are formed on the substrate 80 in this order. Thereafter, the gate insulating film 81 and the interlayer insulating film 87, both of which are positioned above the driver connecting terminal 90, are etched away so that the driver connecting terminal 90 is exposed outside, and then connected with various drivers (drive devices).
(Patent Document 1)
    Japanese Unexamined Patent Application Publication No. 11-133457 (published on May 21, 1999)(Patent Document 2)    Japanese Unexamined Patent Application Publication No. 11-135622 (published on May 21, 1999)(Patent Document 3)    Japanese Unexamined Patent Application Publication No. 6-112485 (published on Apr. 22, 1994)